VHDL design and FPGA implementation of direct torque control for induction machines

Received Mar 9, 2020 Revised Dec 5, 2020 Accepted Mar 30, 2021 This paper presents a VHDL design and an FPGA implementation of a direct torque controller (DTC) used to order induction machines (IM). The use of FPGA at high sampling frequency reduces the torque ripple while maintaining the classical DTC control structure. We have adopted a modular approach, by dividing the global entity into a set of elementary blocks designed and implemented separately. The performances of this command are to reduce the torque ripple to 0.01 Nm and the flux ripple to 0.01 wb with a circuit implementing DTC control of 3,256 LEs of complexity and 64 latency clock cycles. To evaluate the performance of our FPGA circuit implementing DTC controller, we have performed a co-simulation platform based on MATLAB/Simulink and Modelsim programs. MATLAB/Simulink was used to simulate the dynamics of the induction machine associated with its inverter and the proposed DTC control strategy was executed under the modelsim software using the VHDL fixed point. We have operated our circuit FPGA in the loop in a speed variation platform of induction machine and we have obtained the following performances: A zero overrun, response time at speeds of 300 ms and a zero static error as required in the specifications.


INTRODUCTION
The direct torque controller (DTC) is a technique used in variable speed drives of induction machines to control the electromagnetic torque and the stator flux in a simple and decoupled manner, the original structure of conventional DTC was proposed by Takahashi in 1986 [1], the presence of two hysteresis controllers in the structure of this control induces ripples on the flux and the torque. The evolution of power converter technology and the use of DSP or field-programmable gate array (FPGA) for numerical calculations have allowed the development of complex and robust control algorithms and the development of optimal control techniques for (IM) [2].The use of a DSP for the implementation of DTC control algorithms with switching frequencies of 20 kHz [3] does not prevent the presence of torque ripples and deterioration of torque and flux estimates, while the use of an FPGA component allows a reduction of the execution time and consequently a high sampling frequency , this paper proposes a design methodology and implementation of the DTC control of an induction machine on an FPGA target with a high sampling frequency.
Very high-speed integrated circuit (VHSIC) hardware description language (VHDL) was used to describe the behavior of the control algorithms. To get simple implementation and fast computation while minimizing calculation errors and hardware resource usage, we have used a two´s complement fixed-point format, a variable word-size approach and a non-restoring method [4] to calculate the square root operation of stator flux. We have begun this work with a general introduction presenting the context of DTC control and the different methods of its digital implementation either on an FPGA target or on a DSP-based target, indicating the contribution of the FPGA implementation compared to DSP techniques, then we will study in section 2 the principle of the DTC command and the mathematical equations of this control strategy. In section 3, we presented and described the design and the proposed implementation for this command block by block, which we will use later to build the FPGA circuit implementing the DTC. In section 4, a Simulink/Modelsim co-simulation platform is given for the validation of the suggested control strategy, the results of the implementation are presented and discussed, a general conclusion and perspectives for this work are presented at the end of this paper.

THEORETICAL BASIS OF THE DTC AND THE PROPOSED METHOD
The main objective of the DTC command is to estimate in real-time the values of the torque and the magnetic flux according to the currents and the voltages of the machine. This command imposes on the machine, directly and independently, the torque and the flux by choosing the appropriate voltage vector of the inverter in such a way as to maintain the torque and flux errors within the limits of the hysteresis comparator [5], [6].

Determination of the α, β currents and voltages signals
This first block of the DTC command projects into a 2-phase reference frame (α, β) the electrical signals of the induction machine expressed in a 3-phase reference frame (a, b, c) by carrying out the transformation of Concordia [7], [8]. The values of the current signals in this new reference frame (iα, iβ) are obtained from the signals (ia, ib) according to (1), (2) while the current state of the switches of the voltage inverter (Sa, Sb, Sc) and the level of the bus Vdc make it possible to calculate the values of the voltage signals (vα, vβ) by respecting (3), (4).
In order to ensure the orientation of the stator flux, we must know its exact position at all times [10], [11], for this, we divide the trajectory of the flux vector φs into six symmetrical sectors [12], the position of the flux is obtained by calculating the flux angle θs based on the α, β flux components [13] as indicated in the (7):

Hysteresis controllers
The hysteresis controllers allow us to provide the flux and torque error state according to the difference between the reference values and the estimated values. We have chosen to use, as shown in Figure 2, a 2-level hysteresis controller for the flux and a 3-level hysteresis controller for the torque [16], [17].

Switching table
This block generates the appropriate voltage vector (Sa, Sb, Sc), among the six possible active vectors (V1-V6) or the two null vectors (V0, V7), from the inverter optimal switching table [18], presented in Table 1, depending on the current position of the stator flux (expressed by sector) and the flux and torque error state ϕ, τ the outputs of the hysteresis comparator [19].

PROPOSED DESIGN METHOD
The DTC algorithm was designed on the basis of a structural description by adopting the concept of modularity and reusability of the various VHDL blocks of the architecture. We opted during the VHDL design for the use of a two´s complement fixed-point format and variable word size for all arithmetic calculations. The data size of our system starts with 12 bits and increases with mathematical operations to keep good precision without consuming too much hardware resources. Our architecture is composed of seven main parts Figure 3, designed and implemented separately, placing all the blocks inside high-level design using component instantiation, and connecting up all the components to each other using port mapping. the syncpulse block (block A) in charge of the control of all the other DTC blocks in order to have a constant sampling period (Ts), the α, β currents and voltages signals (block B), the α, β flux components (block C), the torque and flux estimator (block D), the Hysteresis controllers (block E), the flux sector detection (block F) and the switching table (block G) which generates the pulses to be applied to the various arms of the inverter. We have adopted a modular approach [20]- [22] to realize our architecture, we will propose, study and validate each module of our design using the FPGA CYCLONE II of Altera EP2C35F672C6 for the implementation and Quartus II software for the compilation and simulation of the different VHDL models. Figure 4 shows the DTC RTL scheme.

Determination of the α, β currents and voltages signals
This block projects into a 2-phase reference frame (α, β) the electrical signals of the induction machine expressed in a 3-phase reference frame (a, b, c). The values of the current signals in this reference frame (iα, iβ) are obtained from the signals (isa, isb) while the current state of the switches (Sa, Sb, Sc) and the level of the bus Vcd make it possible to calculate the values of the voltage signals (vα, vβ) the structure of this block is illustrated in Figure 5. Figure 6 shows the functional simulation of the α, β currents and voltages signals. Currents and voltages signals obtained by this block correspond to the theoretical values given by the Concordia transformation.

α, β flux components
The determination of the flux components φα and φβ is based on (5) and (6), this calculation is carried out in the same way from the signals of currents and voltages α, β. Therefore, only one block has been designed for this calculation and is used twice in parallel. The VHDL model of the α, β flux components is illustrated in Figure 7. Figure 8 shows the functional simulation of the α, β flux components. The flux components evolve in a sinusoidal manner and have maximum amplitude equal to the setpoint.

Flux sector detection
Classical techniques use the CORDIC algorithm to determine the sector of the flux vector [23]. In our architecture we used a simpler method, without any angle calculation, based on simple combinatorial [24] by exploiting the data provided by Table 2 to analyze the flux sectors so as to obtain a more reduced calculation time and low complexity. The VHDL model and the functional simulation of this block are given in Figure 9.

The torque and flux estimator
This block calculates both the amplitude of the flux from (8) and the torque using (9). The nonrestoring method is used to calculate the square root in the expression of the flux, a special architecture has been designed for the squareroot (SQRT). In parallel with this calculation a subtractor generates the difference between the estimated values of flux and torque and the corresponding reference values. The structure of this block is shown in Figure 10. The functional simulation of the torque and flux estimator are given in Figure 11. We notice that the torque and the flux are constant and follow the set point after a very fast transient regime, moreover, the system works with a reduced sampling period, which has allowed us to reduce the torque ripple to 0.01 Nm and the flux ripple to 0.01 Wb as indicated in the results.

The hysteresis comparators
The function of this block is to generate the appropriate error status of the stator flux and torque. The use of 2 and 3 level hysteresis controllers require the representation of their outputs respectively on 1 and 2 bits. The VHDL model and the functional simulation of Hysteresis comparators are given in Figure 12.

The switching table
The appropriate voltage vector (Sa, Sb, Sc) is selected based on the flux and torque error state (hys_torque, hys_flux) from the inverter optimal switching table and depending on the current position of the stator flux (sector_pos). The VHDL model and the functional simulation of the switching table are shown in Figure 13.

The syncpulse block
This block is responsible for controlling all the other DTC blocks, in order to have a constant sampling period and therefore avoid the major drawback of conventional DTC which is known by unpredictable inverter switching frequency. The architecture and the functional simulation for the syncpulse block are shown in Figure 14. The choice of the sampling period must take into account the maximum frequency of the inverter, the latency of the control circuit and the dynamics of the process to be controlled, for our case of study a period of 5 µs satisfying all its constraints.

RESULTS AND DISCUSSION 4.1. Simulink/modelsim co-simulation platform
To validate the proposed FPGA circuit implementing DTC control, a co-simulation was realized with MATLAB/Simulink and Modelsim programs. The MATLAB/Simulink was used to simulate the model of the induction machine associated with the inverter and the VHDL program proposed for the DTC command was executed under Modelsim. Table 3 shows the machine parameters used for simulation. We have operated our circuit in a speed variation platform of induction machines (a resistant torque of 20 N.m is applied to the machine at the instant t=0,4 s), and we have fixed the following performances: A zero overrun, a response time in speeds of 300 ms and a zero static error. In this section we will, first of all, validate the DTC command under MATLAB/Simulink, then we will place our circuit FPGA in the loop in the proposed Simulink/Modelsim co-simulation platform.

Validation of the DTC architecture under MATLAB/Simulink
The simulation of the DTC control established under MATLAB/Simulink has allowed us to validate both the model of the machine and its inverter and also to show the strengths and weaknesses of this command and compare them with those obtained with the command based on the FPGA. Figure 15 shows the architecture of DTC under MATLAB/Simulink. Figures 16 and 17 show the results of the DTC control under MATLAB/Simulink. This command allows a decoupled control of the torque and the flux of the induction machine as illustrated in Figures 16 and 17 but we note that the torque and flux ripples are according to the width of the controller's band and therefore the reduction of this band allows the decrease of the ripples but at the expense of the increase in switching losses.   Figure 18 shows the architecture of the MATLAB/Simulink co-simulation of an asynchronous machine modeled under MATLAB/Simulink associated with an inverter and the proposed FPGA circuit implementing DTC control in the loop. Figures 19-21 show the results of the DTC in the loop. The results obtained, as shown in the Figures 19-21 show the reduction of the ripples on the couple as well as the evolution of the flux in the form of a circle with weak undulations, this thanks to the use of a sampling period fixed (5 µs) and the reduction of the bandwidth of the hysteresis controllers to 0.01 Nm for the torque and 0.01 Wb for the flux, we also note that the current signals Isa and Isb appear as sinusoidal. Figure 21 shows the evolution of the speed. we note that this command allows a zero overshoot, a response time at speeds of 300 ms and a zero-static error with respect to the setpoint and the disturbance.

Performance analysis and effect of the sampling time to torque ripple
The major drawback of conventional DTC is the unpredictable switching frequency of the inverter. Therefore, the amplitude of the hysteresis band must be large enough to avoid excessive switching which causes relatively large torque ripples; our circuit operates with a constant switching frequency. The use of the FPGA target to implement the DTC allowed us to minimize and fix the sampling period. Table 4 represents the FPGA resources available and those consumed by our circuit. The experiment was conducted on CYCLONE II of Altera type EP2C35F672C6 and consumes 3,256 logic elements for the implementation. We have increased the frequency in such a way as to reduce the ripple torque while keeping the same level of complexity as the works [8], [10], [25], [26].

CONCLUSION
In this paper, we have developed and implemented on FPGA a DTC control strategy of an induction motor. The DTC was preferred to other control techniques thanks to its simplicity and its high performance in motor control. Although DTC presents a large ripple on flux and torque signals, it was possible to minimize it to a low value by reducing the sampling period, this reduction was achieved by using FPGA implementation of the DTC algorithm thanks to parallel processing techniques and VHDL programming aimed at reducing the latency of the circuit when approaching a system real-time by the application of a simple architecture for the different blocks of the DTC command and in particular in the torque/flux estimator. We have proposed an FPGA circuit implementing DTC control and we have realized a platform based on MATLAB / Simulink and Modelsim co-simulation of the speed variation of an asynchronous machine. The results obtained enabled us to validate our DTC-FPGA circuit. Comparatively to the conventional DTC controller the proposed architecture has a slight advantage. The obtained performances from this command are 3,256 LEs of complexity and 64 latency clock cycles with the torque ripple equal to 0.01Nm and the flux ripple is 0.01wb. As a forthcoming application, the DTC-SVM control of an induction machine should be performed while exploiting the DTC-FPGA circuit and the co-simulation platform proposed in this paper.