A cascade multi-level inverter topology with reduced switches and higher efficiency

ABSTRACT


INTRODUCTION
In recent years, there has been a lot of interest in multi-level inverters (MLIs) because of their potential uses in industrial and electrical systems, as well as their minimal electromagnetic interference, ease of control, and high efficiency.Additionally, it is possible to link it up to various renewable energy sources such as wind turbines, and photovoltaic solar panels [1]- [8].Since 1970, various topologies have been developed [9].The two-level inverter is the most common type of inverter, and it is named for the fact that it produces two different voltage levels.However, the performance of this inverter is affected by a high level of total harmonic distortion (THD), leading to the need of a large filter size, a high voltage rating for the switches, a high switching frequency, which results in additional switching losses, increased voltage stress on the switches, and electromagnetic interference.The two-level inverter can only be utilized for applications that involve low and medium voltage [10]- [15].This is because the switches have a high voltage rating and are subject to voltage stress.This brings up the requirement for a different configuration.MLI is presented in order to provide a DC/AC conversion that has significantly improved performance and significantly reduced THD [16]- [18].
The best operation of most electrical applications is ensured by using a sinusoidal waveform supply [19]- [21].With an increase in the number of inverter levels, the output voltage becomes more similar to a sinusoidal waveform, hence lowering the THD [22], [23].When compared to the hard-switched two-level ISSN: 2302-9285  A cascade multi-level inverter topology with reduced switches and … (Osama Yaseen Khudair Al-Atbee) 669 pulse width modulation (PWM) inverter, the MLI has a number of advantages, including a lower dv/dt at high power operation and higher efficiency [24]- [26].Generally, there are three main topologies for MLIs: cascade, diode clamp, and capacitor clamp.Among these topologies are the following: the cascade MLI is the simplest to construct and has the fewest number of components [24], [27].Typically, cascade MLI is made up of a number of switches and DC sources that are all connected in series.To generate alternating current voltage with several levels, the switches must be toggled on and off in order to achieve the fundamental voltage and eliminate the higher order harmonics in the output.In this paper, a cascade of MLIs is presented and compared with three inverter topologies to get the fewest number of switches possible to reduce the size and cost of the converter and to reduce switching losses by reducing the number of switches in the on-state during each mode of operation, which improves efficiency.

RESEARCH METHOD 2.1. Conventional cascade bridge MLI topology
Figure 1 depicts the conventional cascade bridge MLI topology that is commonly used [22].The output voltage level of this inverter is: where N represents the number of switches necessary to achieve the desired voltage level.
Figure 1.The conventional cascade bridge MLI

The cascade MLI topologies
The topology for the cascade MLI as a modified topology for the cascade bridge MLI as shown in Figure 2 [28].As can be seen in Figure 2, the number of switches in the level marker part is 5, with three individual DC sources to form two cascade cells connected in series, in addition to the four switches in the H-bridge part.The number of output voltage levels depends upon the number of cells.The number of switches is reduced considerably compared to the conventional cascade bridge MLI for the same output voltage level.To reduce the THD in the output voltage the number of output voltage levels must be increased but this will require more DC sources and switches and need more complex control circuit.The output voltage level of this inverter is: Where N is number of switches and n is the number of DC sources.The 7-level cascade MLI topology in [7] can be improved as shown in Figure 3.In this figure, one of the two switches in each cell is replaced by a diode.The required number of switches and diodes required can be calculated as: The number of diodes = ( − 3)/2 (5) Figure 2. The cascade bridge 7-level inverter Figure 3.The modified 7-level MLI circuit in [7] Gajula [29] shows an amazing topology for cascade MLIs as shown in Figure 4.In this topology the maximum output voltage, the number of individual DC sources, the number of switches and the number of diodes is as in above circuit but in this topology only one switch is at on state in each level of output voltage with a reduced number of diodes in each level that are inversely proportional with number of levels that lead to reduce the losses of the switches and increase the efficiency.

THE TOPOLOGY OF THE PROPOSED CIRCUIT
The proposed cascade MLI circuit is shown in Figure 5.In this topology, the maximum output voltage, the number of individual DC sources, the number of switches, and the number of diodes are as in section c.The main difference in this circuit is that only one diode will work at each level, which is the main difference from the circuit in Figure 4.That means fewer losses and higher efficiency.The proposed circuit operates as follows, and only the first 3 modes of operation will be explained as they will be repeated for the rest of the modes: -At level 1, the load receives energy from the DC source V1 via the switch S5 and the diode D2 on a positive half-cycle basis.For the H-bridge, S1 and S4 are turned on, as seen in Figure 6(a).-At level 2, Energy is received by the H-bridge via the switch S6 and D1 from the DC sources V1 and V2.
Switches S1 and S4 stay on, as seen in Figure 6(b).-At level 3, through the switch S7, the H-bridge receives energy from the DC sources V1, V2, and V3.
Switches S1 and S4 stay on, as seen in Figure 6(c).-At level 4, the load receives energy from the DC source V1 via the switch S5 and the diode D2 on a negative half-cycle basis.For the H-bridge, S3 and S2 are turned on, as seen in Figure 6(d).-At level 5, energy is received by the H-bridge via the switch S6 and D1 from the DC sources V1 and V2.
Switches S3 and S2 stay on, as seen in Figure 6(e).-At level 6, through the switch S7, the H-bridge receives energy from the DC sources V1, V2, and V3.
Switches S3 and S2 stay on, as seen in Figure 6(f).

SIMULATION MODEL & RESULT OF THE PROPOSED INVERTER
The MATLAB/Simulink model of the proposed inverter is shown in Figure 7.The control circuit generates the gate signals for the switches by comparing a three-phase, 12,250 Hz triangular carrier signal with a 50 Hz sinusoidal reference signal, which is accomplished through the use of the PWM approach.The waveforms of the control circuit are illustrated in Figure 8.A cascade multi-level inverter topology with reduced switches and … (Osama Yaseen Khudair Al-Atbee)

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Control pulses for the proposed inverter are generated by a series of logical and mathematical MATLAB functions.Output voltage for the proposed 7-levels inverter is shown in Figure 9.The THD for the output voltage is shown in Figure 10, and it can be seen that the THD is about 21.38 when the modulation index m is 0.95.For the proposed topology, the number of levels is 7, and for comparison with the inverter circuit that was explained in section c of the previous section, the number of switches is the same.Yet, in the proposed circuit, each level requires one diode and one switch to be in conduction mode.Table 1 shows a comparison between the number of switches in the different topologies for seven-level inverters: The reduction in switches used leads to a reduction in the size, weight, and cost and an improvement in the efficiency of the converter.The efficiency is also affected by the number of switches in conduction mode in each level of operation.Table 2 shows a comparison between the number of switches during the onstate in the first three levels of operation for the different circuits shown in the previous section.From Table 2, it can be seen that c-circuit and the proposed circuit have the lowest number of switching devices during the on state.On the other hand, the proposed circuit has only one diode working in each operating mode.The reduction of the number of switches (on-state) in the inverter during the operation modes, as well as the reduction of the on-mode, leads to an increase in efficiency.The effect of the switch reduction becomes more significant when adopting a higher number of levels of output voltage.Figure 11 shows the efficiency comparison for the four topologies adopted in this article.This figure shows that the highest efficiency was obtained in the proposed circuit.

CONCLUSION
In today's applications, MLIs are becoming increasingly important.The proposed inverter has the potential to produce a high-quality output voltage while minimizing losses and increasing efficiency.It outperforms the traditional cascaded multilevel inverter in terms of performance.Switching losses are reduced when the suggested control strategy is used, resulting in increased efficiency.According to the simulation results, the new topology is more efficient than the previous inverters.

Figure 7 .Figure 8 .
Figure 7.The simulink model of the proposed circuit

Figure 9 .
Figure 9.The output voltage of the proposed topology

Figure 11 .
Figure 11.The efficiency comparison

Table 1 .
The number of switches in the different topologies for seven level inverters

Table 2 .
The number of switches in on-mode in the first three levels of operation