Design and implementation reversible multiplexer using quantum-dot cellular automata approach

Rapid progress in the field of nanotechnology includes using quantum dot-cellular automata (QCA) as a replacement for conventional transistor-based complementary metal oxide semiconductor (CMOS) circuits in the construction of nano-circuits. Due to ultra low thermal dissipation, rapid clocking, and extremely high density, the QCA is a rapidly growing field in the nanotechnological field to inhibit the field effect transistor (FET)-based circuit. This paper discusses and evaluates two multiplexer (MUX) architectures: an innovative and effective 4×1 MUX structure and an 8×1 MUX structures using QCA technology. The suggested architectural designs are constructed using the Fredkin and controlled-NOT (CNOT) gates. These constructions were designed to simulate using tool QCA designer 2.0.3. The 591 and 1,615 cells would be used by the 4×1 and 8×1 QCA MUX architectures, respectively. The simulation results demonstrate that, when compared to the previous QCA MUX structures, the suggested QCA MUX designs have the best clock latency performance and use of different gate types.


INTRODUCTION
Data loss is one of the confrontation problems in the development of prototypes and systems.Reversible counting is a probable solution to this problem by letting the counting be done at the logical scale without data loss by establishing the number of inputs equal to the number of outputs [1].The main goal of implementing reversible circuits is to decrease the number of logic gates, garbage outputs, fixed inputs, and quantum costs.The quantum dot cellular automata (QCA) have emerged as a potential computational structure for the modernization of nano computing systems.It has a large ability in the growth of circuits with high space intensities and dispersion of low heat and permits faster computers to develop with lower power consumption.QCA is a new instrument to produce nano-level digital equipment, study and resolve their various parameters.It is also a potential technology for low power and high-intensity memory plans [2].The advantages of QCA are i) lower power because there is no current outflow only energy required to add to raise the electrons from their ground situation [3], ii) quantum cells are very tiny scaled in nano-scale and demands less very less region [4].
The aim of this paper is to suggested QCA designs for reversible multiplexers (MUXs) using a fundamental building block.The fundamental building block can be requested to implement their required gate.It is possible to present the suggested implementation of the MUX to develop quantum gates including controlled-NOT (CNOT) and Fredkin gates (FG) because QCA designs will be utilized as building blocks.It is possible to implement reversible circuits with many quantum gates using fundamental building block.The QCA designer tool, version 2.0.3, has been used to implement and simulate the QCA circuits in this paper.

METHOD
The QCA fundamentals and constructions are introduced first in this section.The reversible gates (Fredkin and CNOT) are then explained, followed by the MUX structure.

Fundamental quantum dot automata construction
On a nanoscale, QCA technology could replace field effect transistor (FET)-based devices [5].Regards to elevation power consumption, finite physical density, and elevation current leakage, complementary metal oxide semiconductor (CMOS) is reaching the transistor finite point in operation [6].By placing charges among quantum dots, QCA is a transistor-free processing technique that encodes binary information [7].
This method is cell-based.As illustrated in Figure 1, each cell has two electrons and four transporters that serve as storage for the electrons.Tunnels are used to carry these electrons from one transporter to another [8].Figure 2 depicts a fourth quantum point QCA.These free electrons are forced to shift to the diagonally reversed locations by their columbic interaction.There are then only two conceivable states, depending on the placement of the electron.This results in two polarizations in the QCA cell [9].The state polarizations are denoted by the numbers -1 for binary zero and +1 for binary one [10].These polarizations in the 0 and 1 states can be expressed as in (1) [11].
Many QCA cells make up the QCA wires, which can be utilized to transmit input cell polarization.Two collections of QCA wire are possible: i) single-layer crossing wires; ii) multiple-layer crossing wires [12].In QCA circuits, two wire types 90 degree and 45 degrees are used.The wire of basis cells that have been rotated by 45 degrees is known as the 45 degrees [13].Inverter gate (NOT) and majority gate (MG) are the two main QCA gates [14], [15].NOT gate and MG (majority gate) are represented in Figures 3(a) and 3(b).MG's neutralizing role is its logical purpose can be expressed as in (2).

Clock of QCA
QCA system contain the clocks that's supply power for automation and for control the flowing data.Cell of QCA has four phases: switch, hold, release, and relax.In case of switch, the cells start un-polarized and with low potential barriers but the barriers are raised during this case.In case of hold ,the barriers are held high [16] every cell fetches polarized after the electrons proceed to the dots which need the lowest energy depending on the driver cell [17] while the case of release, the barriers become low.In last case of relax, the barriers keep low and the cells remain in an un-polarized state [16].Circuit of QCA can be splitted into 4 areas which each area comprises four phases stated in Figure 4 [17].

FG
FG contain three inputs (I1, I2, I3) and three outputs (P1, P2, P3) that swap the last two bits if the first bit is one.It is used as multiplexer (N*1MUX) and out of three inputs, one input used as enable where P1=I1, P2=I1' I2+I1I3, and P3= I3 I1+ I1' I2 [18]. it is also self-reversible as it is its own inverse.It is a prefecture gate because the number of logical ones (hamming weight) of an input is same as its output [19].Figure 5 shows a block diagram of a Fredkin gate and Table 1 demonstrates its truth table.

CNOT gate
CNOT (Feynman) gate is general used for sign copying or to get the supplement of the data flag.It is contain two inputs (I1, I2) and two outputs (P1, P2) where P1=I1 and P2=I1XOR I2 [20], [21].Figure 6 shows a block diagram of a CNOT gate and

MUX
A MUX is an essential piece of equipment in the modeling and simulation of digital memory circuits [22].A combinational circuit really does have multiple inputs (one or more select inputs) but just one output.Signals are passed from one of the inputs to the output.Figure 7 [23], [24] show it.It receives binary information [0,1] from various input lines or sources and routes a specific input line to a single output line based on the set of select lines or sources.A reversible 2 b -to-1 MUX can be implemented using only a 2 b -1 gate, which generates 2 b +b-1 garbage outputs.It also requires a 5(2 b -1) reversible cost and a 5(2 b -1) Λ delay, where b corresponds to the number of selection lines and Λ defines the unit delay [25].
Figure 8 demonstrates a 2x1 MUX block diagram.It has two inputs, one selection, and one output.It is constructed by onereversible FG, with first input being selection (I1) and the second output (P2) being the MUX output.Figure 9 demonstrates a layout of a 2×1 MUX using QCA technique [26].The following (3) [27] can be used to express the output (P2) and the truth table for a 2×1 MUX can be seen in Table 3. Figure 10 illustrates the simulation result of the 2×1 MUX design using 75 cells with 0.18 μm 2 .

PROPOSED MULTIPLEXER
This section is split into two parts: the first presents 4×1 MUX structures that use Fredkin, CNOT reversible gates, and the second part needs an implementation of a new 8×1 MUX using the unique structure suggested in the first part.

4×1 MUX
The 4×1 MUX has four inputs, two selection paths, and one output.Figure 11 demonstrates a suggested 4×1 MUX block diagram.Three Fredkin gates (three 2×1 MUX) and two CNOT gates have been used.Figure 12 demonstrates the layout of a 4×1 MUX using the QCA technique.

8×1 MUX
An 8-to-1 MUX must have eight data inputs, three input select lines, and a single output line.The MUX chooses the inputs based on the selected line combinations.Figure 13 demonstrates a suggested 8×1 MUX block diagram.Seven Fredkin gates (two 4×1 MUX and one 2×1 MUX) and six CNOT gates have been used.Figure 14 demonstrates the layout of an 8×1 MUX using the QCA technique.

SIMULATION AND RESULTS
QCA designer is a simulation software was using to evaluate QCA logic circuits.QCA simulation results are including bi-stable approximation and coherence vector.approximation bi-stable determine the state of a single cell in a time-independent manner using retinal energy neutralization, which determines the cost of two cells with flip polarization, lowering simulation time in this type.Each cell can be worked in 4 steps: input (blue cell), output (yellow cell), fixed (polarization cell), and normal (green cell) seen in Figure 15.The bistable approximation is used to provide input combinations with the parameters seen in the Table 4.The different designs that have previously been designed have been taken into account.Previous designs are compared to a suggested 4×1 and 8×1 MUX.Tables 5 and 6 make a comparison these designs to the suggested design through terms of the area, number of cells, response time, and number of gates used in constructed MUX. Figure 16 illustrates the simulation result of the suggested 4×1 MUX design using 591 cells with 0.93 μm 2 .Figure 17 illustrates the simulation result of the suggested design of an 8×1 MUX using 1,615 cells with 2.95 μm 2 .

Figure 3 .
Figure 3.The primary QCA gates (a) NOT gate and (b) MG gate

Figure 4 .
Figure 4. Clock signal of QCA

Table 2
demonstrates its truth table.

Table 5 .
4×1 MUX result comparison 4×1 MUX Gate types used in design Overall Area (μm 2 ) The number of cells used Response Timein terms clock zones

Table 6 .
8×1 MUX result comparison 8×1MUX Gate types used in design Overall Area (μm 2 ) The number of cells used Response Timein terms clock zones