Bulletin of Electrical Engineering and Informatics

Received Mei 27, 2022 Revised Aug 5, 2022 Accepted Aug 28, 2022 Fast switching techniques at high frequencies are employed for quick charging and energy conversion in electric vehicle (EV) power converters. Electromagnetic interference (EMI) noise is produced due to the fastswitching process, which may result in malfunctioning and degraded EV performance. In this work, a digital chaotic pulse width modulation (DCPWM) technique-based EMI noise mitigation process has been applied to elementary positive output super lift Luo (EPOSLL), two-stage cascaded boost (TSCB), and ultra-lift Luo (ULL) converters, and a comparison study has been conducted with EMI reduction levels as per electromagnetic compatibility (EMC) standards. The duty cycle is varied from 0.5 to 0.67 to get the desired output voltage as an input of 10V to achieve the power ratings of 40 W to 80 W for various load conditions. A total of 4 dBV (3 V) to 15 dBV (10 V) of conducted EMI noise has been mitigated for the abovesaid converters. Simulation results based on power spectrum density and hardware results based on fast fourier transform (FFT) of output voltages are analyzed. According to the findings, the ULL converter is more acceptable for electromagnetic compatibility in EV applications than EPOSLL and TSCB DC-DC converters.


INTRODUCTION
Nowadays compact size solid-state electronic devices-based equipment is occupied in most of the industries and home-based appliances. Further, the design engineers are concentrated on reducing the circuit area and increasing the processing speed by varying the switching frequency rapidly. Due to the above-said reasons, electromagnetic interference (EMI) has been generated and it should be carefully mitigated. Electromagnetic compatibility (EMC) defines a limitation of EMI noise that is generated or radiated from the electronic devices-based circuits when operating at high frequency for the DC-DC conversion process [1], [2]. The classifications of EMC are shown in Figure 1. EMI leads the way to the degradation of nearby devices performance by creating unwanted noise signals in terms of voltage and current. EMI limits as per CISPR-11 for semiconductor components-based circuits are shown in Table 1. EMI filters are designed for the better performance of electric vehicle (EV) converters as per CISPR 11 standards [3], [4]. With the help of active and passive components-based filters are used to select the required signal and to block the unwanted noise which is generated from the conducted EMI source [5]- [9]. Due to external components, the weight and cost have been considered as a drawback. To overcome the drawback of filters, shielding techniques have been promoted. The shielding method is about to cover the entire device or circuit with an enclosure-type metal box to stop the connection with the outside environment for the spreading of EMI noise. Through input ports, display, wires, and output ports the leakage of EMI is possible. Soft switching technique has been procured instead of hard switching to reduce the high switching loss that occurred due to the large dv/dt, di/dt during switching on and off for high frequency on the output of EV converters as shown in Figure 2. The implementation of the soft switching approach needs a greater number of components and it makes the circuit operation complex [10]. After the filter and shielding approach randomization technique comes into the picture. In this technique, with the help of gate pulse modulation like increasing or decreasing the width of pulse,the peak value of the spectrum noise is spread over the entire cycle instead of a sudden increase and decrease. This way the generated EMI has been suppressed.   But generating a random pulse module makes the circuit complicated. Chaotic pulse width modulation technique is derived from random pulse modulation and the DC-DC converters are operated in chaotic mode by incorporating an external circuit that is used to generate chaotic carrier signal [11]- [13]. Analog and digital approaches are the two types of approaches used to generate chaotic carrier waves. The digital approach is mostly used in power converters due to its accuracy, frequency, and amplitude values can be reprogrammable with the help of digital programmable devices. Implementing this approach, the spike of the output voltage has been flattened throughout the total time period and maintaining the total energy constantly and EMI has been reduced. Chaotic pulse width modulation (PWM-based) EMI mitigation process gives better results compared with other EMI mitigation techniques. In EV, DC-DC converters play an important role in the energy conversion process and energy storage. Most of the converters are operating at the high-frequency range to increase the gain based on the duty cycle as shown in Table 2 and the respected chart is also shown in Figure 3. Hence, EMI has been generated. In this analysis, the digital chaotic (DCPWM) technique is applied on single switch MOSFET based high gain converters like elementary positive output super lift Luo (EPOSLL), two-stage cascaded boost (TSCB), ultra-lift Luo (ULL), the respected EMI mitigation values are compared with each other, and the performance of that converters is also discussed. Single switch MOSFET-based converters reduce the cost and complexity of the hardware embedding process. In addition, researchers working in the above converters for EV application or some other applications may concentrate on CPWM based EMI mitigation process to eliminate the nearby devices malfunction due to EMI noises. The present work is systemized as follows, section 2 discusses the study of EPOSLL, TSCB, and ULL converter working and its switching characteristics, section 3 deals with digital chaotic PWM techniques and their implementation using an fieldprogrammable gate array (FPGA) controller. The proposed EMI mitigation method on EPOSLL, TSCB, and ULL converters are presented in section 4, simulation and results are discussed in section 5, section 6 is about hardware setup and its working, concluded this work in section 7.

SINGLE SWITCH MOSFET BASED BOOST CONVERTERS: EPOSLL, TSCB, AND ULL
In EV applications energy conversion is an important area to store as well as to drive the load. Mostly, solid-state DC-DC converters are used for the above-said process with a high gain voltage ratio. The following section explains the various DC-DC converters working and their switching waveforms. Topology comparisons of EPOSLL, TSCB, and ULL are mentioned in Table 3 [14].

Elementary positive output super lift Luo converter
The EPOSLL converter is derived from the Luo converter, which is working based upon the concept of voltage lifting technique [15]. The input is boosted by three times based upon the duty cycle. By increasing the duty cycle ratio, the gain is also increasing. The elementary positive output super-lift Luo converter circuit is consisting of DC supply voltage Vin, 2n capacitors (C1 and C2), n inductor L1, one power switch (n-channel MOSFET) S, (3n-1) diodes (D1, D2), and load resistance R. The circuit operation of the EPOSLL converter and its switching waveforms has explained in the following two conditions as shown in Figure 4: − During ON condition: switch S is in ON state, diode D1 is conducting and D2 is not conducting, capacitor C1 is charged through input voltage Vin and the inductor current IL1 also increases with the

Two-stage cascaded boost DC-DC converter
The two-stage cascaded boost converter circuit consists of three diodes (D1, D2 and D3) two capacitors (C1 and C2), two inductors (L1 and L2) and one MOSFET switch(S) as shown in Figure 5. The boost operation is carried out in two ways, one is through L1, D1, and S and the other way is through C1, L2, and S, in both ways the capacitor C2 is charged and delivers the boosted voltage across the load [16], [17]

Ultra-lift Luo converter
The circuit diagram includes a MOSFET switch S, capacitors (C1, C2), diodes (D1, D2, D3), and inductors (L1, L2) respectively as shown in Figure 6. The parameters of the ULL converter are the input

DIGITAL CHAOTIC PULSE WIDTH MODULATION TECHNIQUE
Spectrum spreading modulation is named chaotic modulation. By adding a disturbance to the PWM modulation controller with the help of an external peripheral device, a chaotic carrier wave signal has been generated. Gate terminals are triggered by chaotic pulses, the harmonics and energy peaks are flattened through the entire time period as shown in Figure 7 and the energy level is constantly maintained. The instant peak value of Fc is tuned to [Fc−Δfc, Fc+Δfc] and the peak of the harmonics and EMI has been reduced [19]- [21].

Randomized carrier frequency modulation with fixed duty
By varying the pulse position or width concerning carrier frequency, chaotic pulses are generated. In the PWM technique normal carried wave is implemented to generate PWM pulses. An abnormal carrier wave 709 is used to generate chaotic pulses with a fixed duty cycle. The switching frequency has been maintained at ±1/3 rd of the central switching frequency 200 kHz i.e. (144 kHz to 266 kHz) for the better EMI mitigation process. The linear feedback shift register has been utilized to achieve the above said RCFMFD [22]. From Figure 8. Tk represents k th cycle duration, αk is the ON state interval, ℇk is the delay time, duty ratio (dk) is given by αk/Tk, k th cycle starting time is ξk and the switching function is q(t). As mentioned in Figure 8, if the k th switching cycle starts at time ξk is given by (1), Here, where uk (t−ξk): single-pulse waveform. The switching function is given in (2): where ( ) value is given by (3):

Pseudo-random number generation using FPGA based linear feedback shift register
A pseudo-random number has been generated for producing switching pulse with the help of linear feedback shift register (LFSR) which is embedded in the FPGA controller as shown in Figure 9. Combination of shift registers and XOR gates embedded in LFSR to do the linear operation for adjusting the clock pulse edges. 2n-1 random numbers are produced by LFSR, where n indicates flip flop counting and the positions of bits are seed and taps. The outputs are 0's and 1's and the LFSR is triggered continuously until the program execution ends by the programmer [23].

Module for generating DCPWM using FPGA controller
The following module explain the generation of DCPWM for 200 kHz switching frequency and the corresponding flow chart also shown in Figure 10. Xilinx design suit 14.7 software has been used to implement the generation of digital chaotic pulses. Verilog language is used to write coding for digital chaotic pulses generation through FPGA controller.
Step 3: Request sub-module from the output of clock frequency.
Step 4: Request LFSR module inputs and outputs to the main module.

Clock frequency generation (5 MHz)
Step 1: Configure the clock inputs fclk and output clk_5M.
Step 3: Set always positive edge pulses.

Feeding data to LFSR module
Step 1: Set input clk, rst and output dout.
Step 2: Set flip flops for 12-bit temp. register and give the 12-bit data value like 0's and 1's.
Step 3: Configure temp. is greater than or equal to 12-bit.
Step 4: Feed the temp 12-bit data.

Variable frequency generation
Step 1: Initialize the inputs fclk, rst, RFS and output Fsw.
Step 4: Set always at positive edge of clock.
Step 5: Configure the load by enabling the counter.

PROPOSED EMI MITIGATION TECHNIQUE ON EPOSLL, TSCB, AND ULL CONVERTERS
The following division gives a picture of the EMI suppression method in periodic and digital chaotic on the various converter. Through line impedance stabilization network (LISN) the input voltage has been given to the converters from the DC source. Periodic and chaotic pulses are given to the MOSFET gate terminals of the above-mentioned converters and the desired output voltage has been calculated with EMI, in the form of power spectrum density through various input voltage levels respectively [24].

Line impedance stabilization network
LISN circuit diagram and its specifications are shown in Figure 11 and Table 4. LISN has been generally used to block the conducted EMI from an outside source through various components like wires, sockets, and display panels. The common-mode and differential-mode noises are measured through various outcomes from the vector sum of line-ground (L-G) and neutral-ground (N-G) voltages.

Digital chaotic PWM based EMI mitigation technique
The proposed digital chaotic EMI mitigation process is as follows. The input of 10 V is given to the converters from a DC power supply (RPS) through LISN are shown in Figures 12(a)-(c). By using the voltage boosting technique, the input voltage is boosted to the desired voltage based upon the gain of the converters. To attain the gain quickly, the switching frequency has been increased and spikes are produced at the instant, in that way EMI has been generated in that circuit. The chaotic pulses have been generated with help of FPGA coding and those pulses are given to the MOSFET switch gate terminal and the generated EMI has been mitigated. The following section explains the EMI mitigation process in periodic and chaotic approach in simulation using MATLAB 2020a and hardware prototype model [25], [26].

SIMULATION RESULTS AND DISCUSSION
The circuit diagrams of the above-said converters are simulated with the help of MATLAB 2020a. The parameters are mentioned in Table 5 for the respected converters. The following section explains the simulation comparison between the periodic PWM approach and DCPWM approach on EPOSLL, TSCB, and ULL converters.

Periodic pulse width modulation technique
The simulated waveforms are shown in Figures 13(a)-(c), the input voltages are varied from 10 V to 12V and the duty cycle varies from 0.5 to 0.67. The periodic pulses are generated by conventional PWM technique with MATLAB 2020a simulink model. The respected inputs and the various outputs of EPOSLL, TSCB and ULL converters are tabulated in Tables 6-8.

Digital chaotic pulse width modulation technique
The chaotic pulses are generated by chaotic mapping technique with MATLAB 2020a Simulink model and applied to the above discussed converters. The input voltages are varied from 10 V-12 V and the duty cycle varies from 0.5 to 0.67 like periodic PWM technique as shown in Figures 14(a)-(c). The various parameter waveforms are captured and shown in Tables 9-11.

Simulation comparison: periodic PWM Vs DCPWM techniques
During the fast-switching process, the frequency range of 150 kHz-200 kHz is applied to the gate terminals of MOSFET to increase the gain, due to that transient occurs in output voltage and output current at the initial stage, in that way EMI has been generated. In that comparison table, at the initial stage, the peak values of various parameters are shown in the periodic and chaotic PWM approach. In the DCPWM technique, the peak value has been spread over the time periodically, through this concept peak value at the initial stage has been minimized compared with the periodic PWM technique. In power spectrum density (PSD) waveform comparison, the density of power spectrum during periodic PWM and DCPWM are calculated. CM noise and DM noise were also compared for periodic PWM and DCPWM techniques. DCPWM technique generated less conducted EMI noise within CISPR 11 limits.

HARDWARE IMPLEMENTATION
From simulation design, the hardware prototype model has been embedded with commercially available components, apart from circuit FPGA spartan 3E controller board has been used to generate periodic and chaotic pulses through coding in Xilinx design suit 14.7 software, and the generated pulses are given to the gate terminal through TLP 350 gate driver circuit.

Periodic PWM and DCPWM approaches
In this approach, periodic and digital chaotic pulses are generated by using an FPGA board and applied to the gate terminals, and the respected FFT of output voltage waveforms are captured with the help of mixed signal oscilloscope (MSO) for EMI analysis as shown in Figures 15(a) Figure 17. There is a variation of 4 dBV to 15 dBV which is equal to 3 V to 10 V (RMS) of conducted EMI has been suppressed in DCPWM technique compared with periodic PWM technique as shown in Table 12 and Figure 18.   Figure 17. Hardware setup for EMI testing Figure 18. Spectral magnitude comparison

CONCLUSION
In this article, the EPOSLL, TSCB, and ULL high gain converter hardware prototype models have been built and tested with designed input and output values with a duty ratio of 0.5 to 0.67 for a power rating

717
of 40 W to 80 W. Calculation of conducted EMI noise has been done by measuring the peak value of PSD in simulation for both cases like periodic and digital chaotic PWM methods at randomly selected peak points. The FFT of the output voltages was also measured randomly throughout the conducted hardware experiment. From hardware results, 4 dBV (3 V) to 15 dBV (10 V) of conducted EMI noise has been reduced in the DCPWM technique on the above-tested converters. From the observations, it can be concluded that the selection of the ULL converter gives better results in simulation and hardware for the DCPWM based EMI mitigation process and satisfies EMC standards than EPOSLL and TSCB converters for EV applications.