Multi-objective optimization of CMOS low noise amplifier through nature-inspired swarm intelligence

ABSTRACT


INTRODUCTION
Almost all wireless communication applications use radio-frequency (RF) integrated circuits (ICs), such as low noise amplifiers (LNAs), in the RF receiver front end to amplify weak signals from receiving antenna to an appropriate level with lower noise. The two important factors that must be addressed when designing LNA are the noise figure and voltage gain [1]. Synthesizing low-noise amplifiers adequately requires many trade-offs between various performance objectives, including voltage gain, noise figure, power consumption, and others [2]. Generally, the main goal of LNA design is to simultaneously achieve two conflicting objectives: low noise figure and high voltage gain at given amount of power dissipation to meet the specification requirements.
Traditional analog design techniques are challenging when optimizing analog circuit characteristics, often requiring many redesign iterations and significant processing time, especially in complex designs where traditional methods may not provide optimal solutions. To overcome these challenges, designers have started using optimization algorithms such as simulated annealing (SA) [3], genetic algorithm (GA) [4]- [7], particle swarm optimization (PSO) [8]- [11], ant colony optimization (ACO) [12]- [17], and artificial bee colony algorithm (ABC) [18]- [21], to improve the design process and achieve desired performance in a reasonable time. However, analog circuit problems usually involve trade-offs between multiple performance characteristics, such as low noise figure and power consumption, stability and phase margin, or power consumption and resolution. Designers must balance these conflicting characteristics to achieve desired performance. For example, in Bulletin of Electr Eng & Inf ISSN: 2302-9285  bandpass filter design, there is a trade-off between selectivity and insertion loss. Similarly, oscillator design requires balancing frequency stability and power consumption. In amplifier design, power output must be traded off against distortion, while in ADC design, power consumption must be balanced with resolution. The above-mentioned techniques have demonstrated their ability to search for optimal parameter, in many applications, including analog design, they can only address a single objective at a time, limiting their effectiveness. To address this limitation, multi-objective optimization algorithms have been developed to provide optimal solutions to design challenges involving multiple conflicting performance characteristics in analog circuits. These algorithms have become an increasingly popular solution to the challenges of analog circuit design [22], [23]. In this work, we describe and apply two of the most used swarm intelligence techniques: the multi-objective particle swarm optimization (MOPSO) and multi-objective artificial bee colony (MOABC) algorithms. We adapt and validate these algorithms through a benchmark of test functions before using them to optimize the voltage gain and noise figure of the RF complementary metal oxide semiconductor (CMOS) low-noise amplifier with inductive source degeneration as a multiobjective optimization problem.
The paper is structured as follows: section 2 provides an overview of the proposed MOABC and MOPSO algorithms. Section 3 discusses the performance validation of the optimization techniques using a benchmark test function. Section 4 describes the low-noise amplifier design. In section 5, we present the optimization results obtained using MATLAB software and the simulation results obtained using the advance design system (ADS) simulator. Finally, we conclude the paper.

AN OVERVIEW OF SWARM INTELLIGENCE TECHNIQUES
This section describes two of the most well-known and commonly used swarm intelligence techniques in the literature that belong to the family of metaheuristics inspired by nature. We will discuss the ABC and PSO algorithms, which will be presented in their multi-objective form.

Multi-objective artificial bee colony algorithm
Although it is a recent technique, the ABC algorithm is increasingly being used thanks to its innovative approach based on the population that has performed well when dealing with various optimization challenges [24]. The ABC algorithm simulates the foraging behavior of a bee swarm, where food sources correspond to potential solutions for an optimization problem. The nectar quantity of a food source indicates its quality as a solution. The ABC comprises employed, onlooker and scout bees. The ABC algorithm follows the main steps outlined: a. Initialization phase The scout bees randomly initialize the food source position and generate external archives by inserting the first non-dominated solutions. b. Employed bee phase Each employed bee locates a new source of nectar (sol i * ) in the vicinity of the current position of its food source ( food i ). Therefore, by comparing the old and new solutions, the best one is chosen and saved in the archive using a greedy selection technique. The food source position is updated by the following equation: Where: i ≠ k ; i ∈ (1,2, … , N); food i k represent the neighbor bee of food i j ; j, k is randomly selected; N represents the number of employed bees. c. Onlooker bee phase The ( food i ), is randomly chosen from the archive generated by the employed bee stage, and the greedy selection is applied to choose the best food source position. The new food source (sol i * ) is produced by the following equation: Where: k ∈ (1,2, … , m) is choosen randomly; while m, represent the archive size; rp is randomly selected from the archive. i ∈ (1,2, … , Food number). d. Scout bee phase In case the solution cannot be improved after a limited number of tries, a scout bee occurs, and the food source position is updated by the following equation:

Multi-objective particle swarm optimization
Eberhart and Kennedy introduced PSO for the first time in 1995 [25]. It is a method inspired by nature, which studied the flocking behavior of birds. A set of particles is referred to as a swarm, and each bird is represented as a particle. Each particle in the decision space uses two types of velocities, pbest and gbest, where pbest is the particle's best location in history, and gbest is the swarm's best previously evaluated location. The PSO method begins by looking for uniformly distributed random solutions. If there are D decision variables, each particle can be represented by a D-dimensional vector, and the velocity ( ) and current position ( ) of the ith particle are represented as [26]: The following information is used by each particle to attempt to change its position: i) current position, ii) distance between pbest and the current position, iii) distance between gbest and the current position, and iv) current velocities. The flowcharts of the proposed algorithms MOABC and MOPSO, are respectively described by the following Figures 1 and 2: The movement of the particle is controlled by updating its position and velocity of the ith particle according to the following expression: With, i=1, 2, …, N and d=1, 2, …, D Where: r1, r2 : random values between 0 and 1 2 : social acceleration coefficient ω : intertia weight 1 : cognitive acceleration coefficient gbest : global best of the particle pbest : personal best of the particle ABC and PSO were adapted to be able to deal with multi-objective optimization problems (MO). Indeed, the goal of the MO approach is to generate a collection of solutions that are not dominated, which are referred to as Pareto optimal solutions for the problem [27]. The figures show the flowcharts of the proposed MOABC and MOPSO algorithms.

VALIDATION OF METAHEURISTICS PERFORMANCE BY TEST FUNCTIONS
To evaluate the performance of the two used algorithms, we chose a multi-objective benchmark consisting of three test functions known in the literature: Zitzler-Deb-Thiele's ZDT1, ZDT2, and ZDT3 [28].
The tests were performed using the MOABC and MOPSO control parameters listed in Tables 1 and 2. Figures 3(a)-(c) shows the pareto fronts of the benchmark test functions generated by the MOABC and MOPSO algorithms. It is clearly seen that the pareto fronts generated by the two proposed algorithms exactly match the true pareto fronts. As a comparison, the MOABC algorithm provides superior performance in terms of optimal quality compared to MOPSO. In fact, the MOABC shows a better distribution of solutions along the front with good regularity. These results show that the proposed optimization techniques can be applied to optimization problems with a guarantee of optimal convergence. In the following, the MOABC and MOPSO algorithms will be applied to the problem of optimal sizing of the LNA.

APPLICATION EXAMPLE: LOW NOISE AMPLIFIER DESIGN 4.1. Low noise amplifier circuit topology and analysis
The cascode topology with inductive source degeneration is the most widely used low-noise amplifier because it can simultaneously satisfy requirements for voltage gain and noise figure [29]. transistor minimizes the effect between the tuned output and input. The biasing circuit is implemented using an M3 transistor connected as a diode. Figure 4(b) illustrates the small-signal circuit of an LNA cascode amplifier, which is used for analyzing noise, including an intrinsic transistor noise model. The input matching network, represented by an inductor (Ls), determines the input impedance of the LNA. To maximize the output power transfer, the output inductor Ld is used to resonate with the output load [30].
In order to determine the expression for noise figure, it is necessary to apply thermal noise theory analysis to identify four distinct noise sources. Subsequently, the impact of these four sources on the output noise power must be determined using small signal analysis. The impact of the common-gate transistor on noise and frequency response is disregarded, along with the parasitic resistances of its D, S, G, and B terminals [31], [32]. In this noise analysis, four sources of noise have been considered: i) the thermal noise of the source resistance ( ̅ , ); ii) the thermal noise of the output resistance ( ̅ , ); iii) the gate noise ( ̅ , ); iv) the channel thermal noise ( ̅ , ).
The impact of the cascode 2 transistor on the noise is insignificant when compared to the main 1 transistor. Furthermore, the noise from the MOSFET's source and bulk resistance is considered minimal and not taken into account for this analysis, as stated in references [33], [34]. The analysis focuses on the four primary noise sources that affect the output, namely ̅ , , ̅ , , ̅ , , ̅ , respectively [35]. The noise sources expressions are summarized in Table 3.
Using the equations listed in Table 3, the noise factor at the resonance is obtaind as (10): Where, With, the white noise factor, intrinsic gate capacitance, correlation coefficient, gate noise parameter, and the sum of Cgs, Cd, and parasitic capacitance are represented by, γ, Cgs, c, β, and Ctot, respectively. The following equations provide the input quality factor Q at the resonance frequency 0 : Where, The gm and gd0 are approximated by the following expression [36].
The length, width, and drain current of MOSFET transistors are represented by L, W, and Id, respectively.

Voltage gain of the low noise amplifier
The first stage provides the input impedance Zin of this architecture at the resonance, Figure 4 Where the input resistance is given by: And at the resonance frequency, The gain of LNA is given by the following equation: Substitute (23) into (24): Where, the gate input inductor, the inductor source degeneration, the operating frequency, the transconductance, the source resistance and gate-source capacitance of M1 transistor, are represented by Ls, Lg, ω0, gm, Rs and Cgs, respectively.

Low noise amplifier design method
The problem of sizing ICs is addressed through multi-objective optimization algorithms and a performance evaluator based on analytical equations. The optimization process generates new sets of design variables at each iteration, including the width and length of transistors, as well as the sizes of resistors, capacitors, inductors, and other components [37]. The design methodology used is described in Figure 5. Two objective functions, namely the voltage gain and noise figure of an LNA circuit, are optimized using MOABC and MOPSO optimization techniques. The voltage gain should be maximized, and the noise figure should be minimized to obtain a good trade-off while respecting the design constraints and target specifications [38], as shown in Table 4.

Optimization results using MATLAB
The MOABC and MOPSO algorithms are applied to simultaneously optimize two objective functions of the LNA circuit: the voltage gains and noise figure. Therefore, the main goal is to minimize the noise figure (NF) and maximize the voltage gain to achieve a good trade-off. Both algorithms have been applied to generate the Pareto front, shown in Figure 6. Table 5 shows three random solutions chosen from the archive of results obtained by the MOABC and the MOPSO algorithms.

Simulation results using advance design system
The ADS simulator is used to simulate the low-noise amplifier circuit to verify the required design performances and specifications.  Table 6 provides insights into the relative errors of the voltage gain and noise figure for two objective functions. The results suggest that the MOABC algorithm delivered the best trade-off solution (Sol@3) with the highest level of consistency between optimization and simulation outcomes. Furthermore, the MOABC algorithm's performance surpassed that of the MOPSO algorithm, as evidenced by the lower relative error values of 22.22% and 29.91%, respectively. Table 7 shows a comparison of the optimization results obtained by the MOABC and the MOPSO techniques and by the other ones reported in the literature [39]- [43]. Therefore, we can notice that the obtained LNA design has a low noise figure and a high voltage gain, compared to other techniques documented in literature.

CONCLUSION
In this paper, we have presented an optimization approach for the optimal sizing of an LNA circuit. The proposed MOABC and MOPSO algorithms were adapted and successfully applied to maximize the voltage gain while minimizing the noise figure of the LNA circuit. The optimized design, implemented in a CMOS 180 nm process, operates at 2.4 GHz with a 1.8 V power supply. The proposed circuit design achieves a better trade-off between voltage gain and noise figure (Gain=21.200, NF=0.848) while consuming less power. The optimized designs were simulated using the ADS simulator to verify the validity of the results achieved by the algorithms. The optimization and simulation values were in agreement, showing the benefits of the proposed design methodology. The results are very promising for helping the designers reduce the number of redesign iterations by only selecting the best design for a specific application. Finally, the achieved LNA design shows better performance than other optimization-based methods previously reported in the literature.