Design of FFNN architecture for power quality analysis and its complexity challenges on FPGA

Prathibha Ekanthaiah, Mesfin Megra, Aswathnarayana Manjunatha, Likhitha Ramalingappa

Abstract


As we all know, power quality (PQ) issues are a major concern these days. Field programmable gate array (FPGA) are essential in PQ analysis, particularly in smart meters for data processing, storage, and transmission. One of the most significant advantages of FPGA is its reconfigurability, with vast hardware resources that can be used to implement complex as well as time-critical data processing units. Because the FPGA architecture supports fixed point arithmetic, data loss occurs in the data path unit, necessitating the realization of the PQ event detection module, and classification model to be more accurate than software implementation algorithms. The majority of the work reported, with feed forward neural network (FFNN) structure occupying large number of multipliers and adders for classification, most of the work reported has not addressed to minimize the data path resources for FFNN instead have addressed in improving classification accuracy. Based on these issues, this paper addresses the implementation challenges in FFNN architecture design by proposing improved and fast architectures. The proposed FFNN architecture design using optimum resources. The FFNN based classifier are designed to perform PQ event detection and classification with 99.5% accuracy. The FFNN processor operates at maximum frequency of 238 MHz.

Keywords


Artificial neural network; Computation complexity; Feed forward neural network; Field programmable gate array; Power quality

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DOI: https://doi.org/10.11591/eei.v11i2.3293

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