Water-inspired WCA optimization of a 180 nm CMOS OTA for ultra-low-power analog interfaces
Abstract
The necessity of ultra-low-power analog front-ends, especially in modern integrated systems, is becoming more evident by the day. Here, we present a two-stage operational transconductance amplifiers (OTAs), in a 180 nm process, with excellent optimization performed using the water cycle algorithm (WCA), which improves the trade-off between gain, speed, and energy. Using continuous migration and precipitation processes from WCA, and through a multi-objective approach, we achieve 80 dB of DC gain, 71.2 degrees of phase margin, and 32.1 volts per microsecond of slew rate (SR) with a total power consumption of 21.3 microwatts. The amplifier demonstrates excellent disturbance rejection with a power supply rejection ratio (PSRR) of 75 dB and a common-mode rejection ratio (CMRR) of 110 dB at 1 MHz. The WCA design methodology is the most precise alternative compared to the other design methods, and is applicable to low-dropout regulators, biomedical sensors, and embedded analog circuits. Our results support the need for the more wide-spread use of nature inspired optimization techniques in analog integrated circuits (ICs) design.
Keywords
CMOS OTA; High immunity (PSRR/CMRR); Low-power consumption; Multi-objective optimization; Water cycle algorithm
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PDFDOI: https://doi.org/10.11591/eei.v15i4.11057
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Bulletin of Electrical Engineering and Informatics (BEEI)
ISSN: 2089-3191
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