Energy-efficient flip-flop design using sense amplifier and clock gating techniques for next-generation IoT nodes

Abstract

A clock-gated sense amplifier-based flip-flop (SAFF) that can operate dependably over a wide voltage and temperature range is suggested in the research paper. The proposed flip-flops (FF) drastically lowers the power and space requirements. Throughout all input data activity variations dependable and low-power operation is made possible by the single-ended latch design and the modified sense amplifier. The design utilization of the proposed SAFF which is made with 90 nm and 65 nm complementary metal-oxide-semiconductor (CMOS) technology is verified by a systematic and conclusive analysis using corner instance simulation for significant process, voltage, and temperature (PVT) variations. In addition, when the data is not changing a clock gating mechanism is employed to minimize the unwanted transition and lower power consumption. When SAFF and clock gated sense amplifier-based flip-flop (CGSAFF) are compared across various CMOS technologies the CGSAFF achieves a much lower delay than the traditional SAFF. The delay decreases from 47 to 6 ps in 90 nm technology and from 60 to 7 ps in 65 nm technology. This shows that CGSAFF outperforms SAFF in terms of speed performance and power efficiency making it more appropriate for portable internet of things (IoT) applications that require low power and high speed.