A Hybrid Hardware Verification Technique in FPGA Design

Abstract

Assertion-based verification (ABV) is best emerging technique for verification of industrial hardware. Property Specification Language (PSL) is one of the most important components of ABV. In this paper we present a method to emulate hardware that is capable of support ABV that in it assertion expressions mapped to HDL. We simulated this method by an applicable example by Modelsim software. Test results indicate that this method performance is good.